Conventionally, electrical design of an electronic substrate has been generally performed by using an electrical design CAD (Computer Aided Design) system for designing an electronic substrate (hereinafter, appropriately referred to as a “two-dimensional electrical design CAD system”) which displays two-dimensionally (hereinafter, appropriately referred to as “2D”) an electronic substrate to be designed.
However, various problems as shown below occurred in recent years in design technique using the two-dimensional electrical design CAD system which two-dimensionally displays the electronic substrate to be designed, and limit of electrical design using the two-dimensional electrical design CAD system was pointed out.
Hereinafter, such various problems will be explained, and description will be made first for a case of performing electrical design having differential wiring in a substrate having a multilayer structure.
It is to be noted that the differential wiring is a wiring technique of wiring two clock signals whose polarities are inversed in a pair, by which electromagnetic wave noise that occurs in the case of wiring by one clock signal can be reduced.
Herein, FIG. 1(a) shows a view illustrating a display example of substrate display on a 2D design screen in the two-dimensional electrical design CAD system as a display example of the two-dimensional electrical design CAD system. The 2D design screen displays the entire electronic substrate being designed on the two-dimensional electrical design CAD system.
Further, FIG. 1(b) shows a view illustrating a part of FIG. 1(a) in an enlarged manner. The view shown in FIG. 1(b) shows a differential wiring area on the 2D design screen shown in FIG. 1(a) in an enlarged manner.
Furthermore, FIG. 1(c) shows a view illustrating the cross-section of the 2D design screen in line IC-IC shown in FIG. 1(b).
As described above, FIG. 1(b) shows the differential wiring area in an enlarged manner, and as shown in the cross-sectional view of FIG. 1(c), a wiring A is a wiring pattern arranged for a first layer of a multilayer substrate, and a wiring B is a wiring pattern arranged for a second layer of the multilayer substrate.
Specifically, the wiring A and the wiring B are differential wiring patterns each of which is severally arranged on different layers.
Incidentally, on the 2D design screen displayed by the two-dimensional electrical design CAD system, even in the case of handling a multilayer substrate in which a plurality of substrates are stacked, a state viewed from an arrow D direction shown in FIG. 1(c), that is, only the plan views seen from above the substrate shown in FIG. 1(a) and FIG. 1(b) were displayed.
Then, in the display mode of the two-dimensional electrical design CAD system, the surface of the first layer is displayed on the 2D design screen and the second and further layers are displayed in a state hidden by the rear surface of the wiring pattern or the like arranged on the first layer, for example.
Therefore, regarding a region shown by numerical character C where the wiring A and the wiring B are overlapped in FIG. 1(b), the wiring A is preferentially displayed on the screen.
Thus, the entire wiring A is displayed, but since the wiring B is positioned on a layer under the wiring A, only areas of the wiring B which are not overlapped with the wiring A in a planar view seen from above the substrate are displayed.
Specifically, since display is performed by the above-described method on the 2D design screen, the wiring B is not displayed for the region C of FIG. 1(b), for example, so there was a problem that even if the wiring B is disconnected whether or not the wiring B is disconnected could not be judged instantly on the 2D design screen.
Further, as another problem which could occur in the region C of the wiring B, there was a problem that, in the case where an instruction is given that a wiring width (pattern width) of the wiring B be designed in the same wiring width of a wiring width (pattern width) of the wiring A, for example, even if the wiring width of the wiring B is designed in a width narrower than the wiring width of the wiring A, which is different from the instruction, the wiring B is hidden by the wiring A and cannot be checked only by viewing the 2D design screen, and whether or not design was performed according to the instruction could not be judged instantly on the 2D design screen.
Next, referring to FIGS. 2(a)(b)(c)(d), another problem in differential wiring will be explained.
Herein, FIGS. 2(a)(b) show a state where a pair of clock signals is wired on the first layer and the second layer of the multilayer substrate.
More particularly, FIG. 2(a) is a view showing the 2D design screen (2D design screen A) in the case where differential wiring is conducted extending across the first layer and the second layer, and FIG. 2(b) shows a cross-sectional view on line IIB-IIB of the 2D design screen A shown in FIG. 2(a).
As shown on the 2D design screen A of FIG. 2(a), it is difficult to specify from two-dimensional display to which wiring layer the differential wiring is wired.
However, in the differential wiring of FIG. 2(a), the wiring A is disposed on the first layer and the wiring B is disposed on the second layer as shown in FIG. 2(b), and herein, consideration is given to a case where each of the wiring layers of differential wiring made up of the wiring A and the wiring B is changed to the second layer and a third layer.
FIG. 2(c) is a view showing a 2D design screen (2D design screen B) after changing the wiring layers of differential wiring of the wiring A and the wiring B such that the wiring A is wired to the second layer and the wiring B is wired to the third layer.
Further, FIG. 2(d) shows a cross-sectional view on line IID-IID of the 2D design screen B shown in FIG. 2(c).
As in the cross-sectional view shown in FIG. 2(d), even if a designer instructed processing of moving the differential wiring between layers to change wiring layers, the fact that the differential wiring moved between layers cannot be visually judged on the actual 2D design screen B as shown in FIG. 2(c).
Specifically, as it is clear when the 2D design screen A is compared with the 2D design screen B, there is no change on the 2D design screen display even if the wiring layers of the differential wiring moved between layers, so there was a problem that the change could not be judged visually.
Now, as a technique of checking wiring layers of the differential wiring as described above, checking a disconnection area of wiring, or checking of design error possibility, a method other than the method by visual observation on the 2D design screen can also be used. For example, judgment can be made by checking a design state using a tool for checking a problem area on another screen, but the method required labor that screens had to be switched for checking each time when checking is performed.
For this reason, as a technique of avoiding the above-described problem, a technique is proposed in which wiring patterns are displayed in different colors for each wiring layer, and wiring layers are discriminated based on color of the wiring pattern.
However, in the case of displaying wiring patterns in different colors for each wiring layer, the designer needs to remember colors of the wiring patterns corresponding to all layers.
For this reason, in the case where the number of wiring layers is as many as 10 layers, for example, there is a fear that the designer could have lapse of memory or the like for the colors of wiring patterns, which caused a new problem that the designer could judge a wiring layer by mistake due to the lapse of memory or the like.
Further, when the number of wiring layers increased, a case could occur where types of usable colors exceeds a limit, and there was also a problem that measures had to be taken in such a case that the same colors were used twice, which made the judgment of wiring layer difficult.
Furthermore, even if the above-described discrimination by colors is applied, when a region where the wiring B cannot be seen exists as in the region C shown in FIG. 1(b) where the wiring A overlaps the wiring B, problems such that a wiring layer of each wiring, disconnection of wiring, a design error of pattern width or the like cannot be instantly checked are not overcome.
Next, as a problem of the design technique using the two-dimensional electrical design CAD system, a problem in an electrical design technique of mounting electronic components mounted on the surface of the electronic substrate into the electronic substrate, that is, on an inner layer of the electronic substrate will be explained.
It is to be noted that the electrical design technique is an electrical design technique of making an area of the electronic substrate smaller to enable high-density mounting by embedding electronic components in the inner layer of the electronic substrate including a multilayer layer constitution.
Then, an electronic component which is embedded in the inner layer of the electronic substrate and built in the electronic substrate is referred to as a “substrate-embedded component”, and an electronic substrate in which electronic component is built is referred to as a “component-embedded substrate”.
Herein, FIG. 3(a) shows a view illustrating a display example of substrate display on the 2D design screen of the two-dimensional electrical design CAD system as a display example of the two-dimensional electrical design CAD system. The 2D design screen displays the entire electronic substrate being designed on the two-dimensional electrical design CAD system.
Further, FIG. 3(b) shows a view illustrating a part of FIG. 3(a) in an enlarged manner. Specifically, the view shown in FIG. 3(b) illustrates a part of the 2D design screen shown in FIG. 3(a) in an enlarged manner.
Furthermore, FIG. 3(c) shows a view illustrating a cross-section of the 2D design screen shown in FIG. 3(b) on line IIIC-IIIC.
As described above, FIG. 3(b) shows a part of the substrate surface in an enlarged manner, in which an electronic component A is arranged on the surface of the electronic substrate, and the electronic component A is connected by a wiring pattern. Specifically, the electronic component A is arranged on the first layer of the electronic substrate equipped with a multilayered layer constitution, and connected by the wiring pattern.
Explanation will be made below for a work procedure of processing of moving the electronic component A to an inner layer of the electronic substrate, that is, a fourth layer (refer to FIG. 3(c)) to make the electronic component A a substrate-embedded component, in the two-dimensional electrical design CAD system, referring to FIGS. 4(a) to (i) which are display examples of the 2D design screen of the two-dimensional electrical design CAD system.
It is to be noted that FIG. 4(a) shows a cross-sectional view on line IVA-IVA shown in FIG. 4(b), that is, a cross-sectional view of an electronic substrate made up of 5 layers shown in FIGS. 4(b) to (i).
As described above, the electronic component arranged for the first layer of the electronic substrate is moved to the fourth layer, and in order to move the electronic component A from the first layer to the fourth layer, the first layer of the electronic substrate is selected first as a processing target of the two-dimensional electrical design CAD system, and displayed on the 2D design screen of a display device.
Then, electronic component data of the electronic component A arranged on the first layer and wiring data of a wiring pattern connected to the electronic component data are selected (refer to FIG. 4(b)), and the selected electronic component data and wiring data are deleted (refer to FIG. 4(c)).
Next, to secure a cavity for incorporating the electronic component A, the second layer of the electronic substrate is selected as a processing target of the two-dimensional electrical design CAD system and the layer is displayed on the 2D design screen of the display device, and cavity data of the cavity for incorporating the electronic component A is arranged on the second layer (refer to FIG. 4(d)).
Herein, the cavity is space generated by forming a hollow or a hole in the electronic substrate in order to embed an electronic component in the electronic substrate, and the electronic component is mounted in the cavity being the space. Then, after mounting the electronic component into the cavity, resin is flowed into the cavity to fix the electronic component, that is, a substrate-embedded component in the cavity.
Next, to secure a cavity for incorporating the electronic component A, the third layer of the electronic substrate is selected as a processing target of the two-dimensional electrical design CAD system and displayed on the 2D design screen of the display device, and cavity data of the cavity for incorporating the electronic component A is arranged on the third layer (refer to FIG. 4(e)).
Next, the fourth layer of the electronic substrate is selected as a processing target of the two-dimensional electrical design CAD system and displayed on the 2D design screen of the display device, and electronic component data of the electronic component A is arranged on the fourth layer (refer to FIG. 4(f)).
Next, to connect the electronic component data of the electronic component A mounted on the fourth layer to the wiring data of a wiring pattern to be wired to the first layer, the second layer of the electronic substrate is selected as a processing target of the two-dimensional electrical design CAD system and displayed on the 2D design screen of the display device, and via data of a via connected to a terminal of the electronic component data of the electronic component A being a substrate-embedded component is arranged into the cavity (refer to FIG. 4(g)).
Next, by selecting the first layer of the electronic substrate as a processing target of the two-dimensional electrical design CAD system to display the layer on the 2D design screen of the display device and arranging the via data on the first layer, the data is connected to the via data formed in the processing shown in FIG. 4(g) (refer to FIG. 4(h)).
Next, the wiring data of the wiring pattern which was deleted in the processing shown in FIG. 4(c) is arranged, and the data is connected to the via data arranged in the first layer for rewiring (refer to FIG. 4(i)).
A component-embedded substrate created according to the above-described work procedure, that is, the electronic substrate in which the electronic component A is built as a substrate-embedded component is shown in FIG. 5(a).
It is to be noted that FIG. 5(a) shows the 2D design screen displaying a substrate having an embedded component, and FIG. 5(b) shows a cross-sectional view on line VB-VB shown in FIG. 5(a).
Specifically, in the case where the above-described processing, which was explained referring to FIGS. 4(b) to (i) is conducted, data of the component-embedded substrate equipped with the constitution of the cross-sectional view shown in FIG. 5(b) is created as a result. In the electrical design by the two-dimensional electrical design CAD system, design is performed referring to the 2D design screen shown in FIG. 5(a), and in the case where the first layer is displayed as in FIG. 5(a), for example, only vias and wiring patterns which are arranged on the first layer are displayed, and data of the cavity and the electronic component A arranged on the inner layer as to on which layer and at what height they are formed cannot be instantly checked.
Specifically, in the case of performing processing of mounting an electronic component, which was mounted on the surface of the electronic substrate, on the inner layer of the electronic substrate, whether or not the electronic component was arranged on a right layer cannot be checked visually on the 2D design screen by the two-dimensional electrical design CAD system, and it took labor and time to judge whether or not the electronic substrate was correctly designed.
Now, in checking a three-dimensional shape of electrical design data in a conventional two-dimensional electrical design CAD system, data for three-dimensional display use added with height information to the two-dimensional electrical design data was generated, and displayed on a viewer.
Specifically, in the case of displaying conventional two-dimensional electrical design data in a three-dimensional shape, the shape needs to be displayed by software for three-dimensional display use which is different from the two-dimensional electrical design CAD system, and it was possible to check the three-dimensional shape of the electronic substrate only on such a viewer.
Further, the above-described software for three-dimensional display use supports display only and cannot edit data, so that editing of electrical design data needs to be performed on the two-dimensional electrical design CAD system, and in order to check electrical design data after editing in the three-dimensional shape, it was necessary to repeatedly perform a work of generating data for three-dimensional display use again and checking the data by the software for three-dimensional display use.
As described, in substrate design by using the conventional two-dimensional electrical design CAD system, much labor and time was required for performing electrical design of the electronic substrate while checking the three-dimensional shape, which caused deteriorated design efficiency.
Specifically, as explained above in various ways, in performing design of differential wiring in which wiring is performed extending across vertical two layers, design of a component-embedded substrate in which components are built inside a multilayer substrate, or the like by using the conventional two-dimensional electrical design CAD system, it is difficult and also takes labor to grasp a state of inner layers on the 2D display screen, so there was a problem of design environment that long time was required for design and a design error easily occurred.
Further, in a conventional two-dimensional electrical design CAD system, there was a problem that electrical design data could not be displayed in a three-dimensional shape and exclusive software or the like was required, and data editing could not be performed in the state where data was displayed in a three-dimensional shape.
It is to be noted that the example explained above merely a part of design example using the two-dimensional electrical design CAD system. Since there is a limit in performing electrical design of the electronic substrate that becomes more complicated every year by the two-dimensional electrical design CAD system, design environment and design technique capable of reducing a design error and easily performing complicated electrical design in recent years have been strongly desired.
It is to be noted that prior art that the present applicant knows at the point of filing a patent is not an invention known to the public through publication, so there is no prior art document information to be described in the present specification.